FIGS. 1A to 1E are cross sectional views illustrating a prior art method of manufacturing a conventional MOS transistor. Referring to FIG. 1A, an active region where a MOS transistor is to be formed is defined by forming isolation layers 110 in a p-type semiconductor substrate 100. Next, a gate insulating pattern 120 and a gate 130 are sequentially formed on the active region of the substrate 100. The active region under the gate 130 serves as a channel region.
Referring to FIG. 1B, in order to reduce the short channel effect, a first ion implanting process is performed to form halo impurity regions 141 in a vicinity of the channel region under the gate 130. The halo impurity regions 141 are formed in the first ion implanting process by implanting p-type impurities in a tilted direction (the directions of the arrows in FIG. 1B) with respect to the substrate 100.
Referring to FIG. 1C, a second ion implanting process is performed to form source/drain extension regions 142, (i.e., lightly doped drain (LDD) regions) within the substrate 100 on opposite sides of the gate 130. The second ion implanting process is performed by implanting lightly doped n-type impurities in a vertical direction (the direction of the arrows in FIG. 1C) with respect to the substrate 100. In some cases, the second ion implanting process may be performed prior to the first ion implanting process. In addition, although not shown in the figure, an oxide layer may be formed as an ion implanting buffer layer on the surface of the substrate 100 prior to the second ion implanting process.
Referring to FIG. 1D, gate spacers 150 are formed on opposite side walls of the gate 130. Next, a third ion implanting process is performed to form source/drain regions 143 within the substrate 100 at opposite sides of the spacers 150 by implanting heavily doped n-type impurities in the vertical direction (the direction of the arrows in FIG. 1D) with respect to the substrate 100.
Referring to FIG. 1E, a silicide process is then performed to form metal silicide layers 160 on the source/drain regions 143 and the gate 130.
In a conventional MOS transistor, (e.g., a transistor used as a logic device), the junction capacitance between the halo impurity regions 141 and the source/drain extension regions 142 reduces the switching speed. However, the junction capacitance cannot be completely removed due to the structural characteristics of the device. Therefore, there is a demand for reducing the junction capacitance as much as possible.